1. Field of the Invention
This invention relates generally to a semiconductor DRAM memory cell and more specifically to an improved semiconductor DRAM memory cell and a method for making the same.
2. Description of the Prior Art
FIG. 1 illustrates a high-capacity dynamic random access memory (DRAM) cell structure. The high-capacity DRAM cell structure 50 has two double level polysilicon cells 20.sub.1, 20.sub.2, each of which includes an access transistor 21 and a storage capacitor 22. In the figures, a single number without a subscript refers to like features in each of cells 20.sub.1, 20.sub.2 since the cells generally have mirror symmetry about the center of source region 13. For example, cell 20 refers to both cells 20.sub.1 and 21.sub.2.
DRAM cell 20 has a pocket 13 of N+ conductivity type formed in a P- conductivity type (P- type) semiconductor substrate 10. Pocket 13, which is part of a diffused bit line, functions as the source for access 21 transistor in both cell 20.sub.1 and cell 20.sub.2.
A deep P-type conductivity implant region 11, typically a boron implant, and a shallow N-type conductivity implant region 12, typically an arsenic implant, are each formed a selected distance from edge 13A of source region 13. The distance from edge 13A of source region 13 to edge Y of N-type conductivity implant 12 is the channel length of access transistor 21. P implant isolation region 14, a channel stop region, and field oxide region 15 are formed on the periphery of DRAM cell 50. A thin dielectric layer 18 overlies implant regions 11, 12, and field oxide region 15. A gate oxide layer 27 overlies source region 13 and the channel region. A first polysilicon layer 16 is formed on dielectric layer 18 over field oxide 15 and arsenic implant region 12 and boron implant region 11. First polysilicon layer 16 functions as a storage electrode for capacitor 22 of cell 20. A transfer gate 19 is a second polysilicon electrode that is separated from the first polysilicon electrode by silicon dioxide layer 17 and from the channel region and source 13 by silicon dioxide layer 27.
The double level polysilicon DRAM memory cell, as illustrated in FIG. 1, is widely used in DRAM arrays because the cell size is significantly reduced over other conventional charge storage DRAM cells.
The threshold voltage of transistor 21 is a function of the effective channel length and the coupling of capacitance arsenic region 12 to polysilicon transfer gate 19. Therefore, variations introduced in either the effective channel length or the coupling of capacitance region 12 and transfer gate 19 by fabrication processes reduce yield because the process variations change the coupling in cells 20.sub.1, 20.sub.2 which in turn results in different threshold voltages for cells 20.sub.1, 20.sub.2.
Cells 20.sub.1 and 20.sub.2 (FIG. 1) are fabricated on a semiconductor chip having many thousands of similar cells and successful operation of the chip requires that all such cells on the chip be free of defects. However, the standard process for forming DRAM cells 20 in a memory array frequently results in an unwanted structure that shorts gates 19.sub.1, 19.sub.2 in cells 20.sub.1, 20.sub.2.
This problem is best understood by considering the fabrication steps used to form prior art DRAM cells 20. The ion implantations used to form capacitance regions 11, 12 in substrate 10 are omitted because these steps are unrelated to the failure mechanism. As shown in FIG. 2, the substrate 10 has P implant isolation region 14 which is overlain by field oxide region 15. A thin silicon oxide layer 18A, typically about 50 .ANG. thick, is formed on substrate 10 between field oxide regions 15 which in turn is covered by a silicon nitride layer 18B, typically about 100 .ANG. thick, which also overlies the field oxide regions 15. After formation of silicon nitride layer 18B, polysilicon layer 16 is formed which in turn is overlain by a sacrificial oxide layer 40.
After formation of oxide layer 40, a photoresist mask 41 (FIG. 3) is formed on oxide layer 40 with opening 42 that is used to define the extent of capacitance electrode 16 of DRAM cell 20 (FIG. 1). As oxide layer 40 (FIG. 3) is etched, photoresist mask 41 is undercut as shown in FIG. 4. Photoresist mask 41 is subsequently stripped using a wet etch process leaving the structure illustrated in FIG. 5.
Etched oxide layer 40 is used as a mask for a wet etch of capacitance polysilicon layer 16 to form the structure shown in FIG. 6. Sacrificial oxide layer 40 is then removed to leave the structure of FIG. 7. Hence, starting with opening 42 in photoresist mask 41, the extent of capacitance storage electrode 16 was defined by the subsequent etching processes of oxide layer 40 and polysilicon layer 16.
The shape of edge surface 16C of capacitance electrode 16 was formed by the wet etch of capacitance polysilicon layer 16 and angle .gamma. between bottom surface 16A of gate 16 and edge surface 16C is determined by the etching process. Angle .gamma. is typically in the range of about 90.degree. to about 60.degree. with a typical angle being about 80.degree..
The steep inclination of edge surface 16C is one factor that limits the yield of prior art DRAM cells 20. Oxide layer 17 is formed over polysilicon layer 16. Oxide layer 17 forms a protruding lip 17A as shown in FIG. 8. Lip 17A is the structure which directly contributes to creation of the failure mechanism for DRAM cell 20. Lip 17A extends around the perimeter of elliptical opening 43 (FIG. 8).
After formation of oxide layer 17, a triple-etch, using oxide layer 17 as a mask, is used to remove dielectric layers 18A, 18B between oxide layer 17.sub.1, 17.sub.2 so that surface 10.sub.1 of substrate 10 is exposed. Gate oxide 27 is grown on surface 10.sub.1, and then the entire structure is overlain by a polysilicon layer 19A (FIG. 9). A mask and a plasma etch are typically used to form gates 19 (FIG. 10) from polysilicon layer 19A.
While the plasma etching removes polysilicon layer 19A over source region 13 (see FIG. 1), polysilicon 19B under lip 17A remains because the plasma etch is shielded from this area by lip 17A.
Accordingly, gate structures 19.sub.1, 19.sub.2 are connected by polysilicon 19B and DRAM cells 20.sub.1, 20.sub.2 are electrically shorted through gate 19.
Hence, the steep inclination of edge surface 16C of capacitance polysilicon results in protruding lip 17a being formed in overlying oxide layer 17 which in turn results in a failure mechanism for the associated DRAM cell. This failure mechanism is a function of the prior art processing steps so that to obtain increased yield, two additional processing steps are required. To remove polysilicon 19B requires another mask step and an isotropic etch so as to break polysilicon 19B in two places. These additional processing steps while increasing yields also increase processing costs and processing times.